This application claims priority from Korean Application, entitled xe2x80x9cHigh Voltage Generation Circuitxe2x80x9d Application No. 2000-36944 and filed on Jun. 30, 2000 and incorporates by reference its disclosure for all purposes.
1. Field of the Invention
The present invention relates to a high-voltage generation circuit and in particular, to a high-voltage generation circuit which is capable of sequentially enabling a high-voltage pump to obtain high-precision pumping, to thereby generate a stabilized high voltage.
2. Description of the Prior Art
In a semiconductor device using an external power supply, a high-voltage generation circuit is widely used. Because the high-voltage generation circuit generates a voltage higher than the external power supply of the threshold voltage of a transistor, the circuit can compensate for a loss of threshold voltage.
FIG. 1 is a schematic block diagram of a conventional high-voltage generation circuit. As shown in this FIG., a conventional high-voltage generation circuit includes a high-voltage level detection unit 1, a high-voltage pump control unit 2, an oscillator 3, a plurality of high-voltage pumps 41, 42-4N, and a high-voltage clamping unit 5.
The high-voltage level detection unit 1 detects an input of voltage VPP and generates both a detection signal DET to produce a stable voltage of VPP and a clamping active signal CLMP. High-voltage pump control unit 2 generates a high-voltage pump control signal VPPEN in response to detected signal DET from high-voltage level detection unit 1.
In response to the high-voltage pump control signal VPPEN, oscillator 3 generates both a pulse signal OSC for driving the plurality of high-voltage pumps 41, 42-4N, and a pump active signal PACT for controlling pumps 41, 42-4N. Pumps 41, 42-4N then pump to obtain a high voltage level under the control of the pulse signal OSC and the pump active signal PACT. High-voltage clamping unit 5 operates to clamp the level of high voltage based on the clamping active signal CLMP from high-voltage level detection unit 1.
FIG. 2 is a detailed block diagram of one of the plurality of high-voltage pumps 41, 42-N shown in FIG. 1. In FIG. 2, a high-voltage pump 41 includes a first NAND gate ND1, a first through a fourth NOR gate NOR1 to NOR4, a first through a fourth precharge capacitor C1 to C4, a first and a second NMOS transistor NM1 and NM2, and a first and a second PMOS transistor PM1 and PM2. Specifically, the first NAND gate ND1 performs a NAND operation on an inverted pump active signal PACT signal from first inverter INV1 and the pulse signal OSC.
First NOR gate NOR1 performs an OR operation on the output of first NAND gate ND1 and the outputs consecutively processed through second inverter INV2. Second NOR gate NOR2 and a fourth inverter INV4 outputs the resultant data signal to a third inverter INV3 through NOR1. Second NOR gate NOR2 performs an OR operation on the output of third inverter INV3 and the output of second inverter INV2, and outputs the resultant data signal to fourth inverter INV4.
Third NOR gate NOR3 performs an OR operation on the output of third inverter INV3 and the output of a fifth inverter INV5. INV5 operates to invert the output of the third inverter INV3, and the resultant data signal is output as first pump driving signal G1. Fourth NOR gate NOR4 performs an OR operation on the output of fourth inverter INV4 and the output of a sixth inverter INV6. INV6 functions to invert the output of fourth inverter INV4, and the resultant data signal is output as a second pump driving signal G2.
A first precharge capacitor C1 precharges the high-voltage pump based on first pump driving signal G1 from third NOR gate NOR3. A second precharge capacitor C2 precharges the high-voltage pump based on second pump driving signal G2 from fourth NOR gate NOR4. A third capacitor C3 pumps the high voltage based on output R1 of third inverter INV3, and a fourth capacitor C4 pump high voltage based on the output R2 of fourth inverter INV4.
A first NMOS transistor NM1 is configured to enable the output of first precharge capacitor C1 to precharge the high-voltage pump by using an external supply voltage VEXT. A second NMOS transistor NM2, is configured to enable the output of second precharge capacitor C2 to precharge the high-voltage pump by using the external supply voltage VEXT.
A first PMOS transistor PM1, having a gate coupled to a precharged node of second NMOS transistor NM2 functions to transmit the high voltage to a Vpp node. A second PMOS transistor PM2, having a gate coupled to a precharged node of first NMOS transistor NM1 operates to transmit the high voltage. In one embodiment, PM1 and PM2 transmit the high voltage at different times, according to, for example, the signal OSC.
A detailed explanation of the operation of a conventional high-voltage generation circuit follows. First, the level of high voltage is reduced, over time, to a non-conforming level. High-voltage level detection unit 1 outputs a detected signal DET smaller (i.e., less) than the internal power supply VDD, which is the core power supply of the DRAM.
Accordingly, high-voltage pump control unit 2 outputs a high-voltage pump control signal VPPEN at a high level (e.g., VDD). Accordingly, oscillator 3 outputs pump active signal PACT at a low level (i.e., a low logic level such as Vss) and pulse signal OSC at a periodic low level.
Each of the plurality of high-voltage pumps-41-4N function to simultaneously perform a voltage pumping operation in response to pump active signal PACT and pulse signal OSC.
FIGS. 3A and 3B are timing views illustrating the operation of a conventional high-voltage generation circuit. As shown in FIGS. 3A and 3B, the high-voltage level (e.g., VPP) is greatly increased each cycle of the pulse signal OSC of oscillator 3. If the high voltage increases to a certain high level beyond maximum level of voltage, detected signal DET from detection unit 1 initiates high-voltage pump control signal VPPEN logic low, thus disabling the plurality of high-voltage pumps 41-4N to halt charge pumping.
In this case, the high-voltage level is sequentially reduced over time and is quickly dropped down into a conforming or acceptable range of high-voltage levels during an active mode rather than during a standby mode.
As mentioned above, if the high voltage level drops to a level less than a certain level, the procedure discussed above is repeated to recommence the voltage pumping.
Conversely, if high voltage rises to a level higher than a maximum high voltage level, high-voltage level detection unit 1 enables the clamping active signal CLMP to perform the clamping operation, preventing the high-voltage level from rising excessively. The use of high-voltage pumps 41-4N is well-known in the art and therefore, a description of their operation is omitted.
As shown in FIG. 3B, the conventional high-voltage generation circuit described above simultaneously activates the plurality of high-voltage pumps 41-4N, and the high-voltage level VPP rises in a chopping wave fashion during one cycle of the pulse signal OSC of oscillator 3.
At the instant high-voltage pump control signal VPPEN transitions to a logic low, the pulse signal OSC of oscillator 3 transistors to a logic high to allow the plurality of high-voltage pumps 41-4N to be simultaneously activated. As a result, an increase in the high-voltage level is produced.
During an actual pumping operation, after high-voltage level is detected, feedback to the high-voltage pump control signal VPPEN causes a delay, resulting in an increased voltage that exceeds a desired maximum high-voltage level.
Accordingly, the conventional high-voltage generation circuit suffers from the drawback that if the high-voltage level is greatly varied, an excessive level of stress may be applied to the memory cell causing a back-bias voltage variance. Such a variance is due to the coupling of well capacitance and results in a degraded cell refresh property.
The present invention provides a high-voltage generation circuit which is capable of sequentially activating a plurality of high-voltage pump circuits, thereby precisely maintaining a level of high voltage within a small range of voltage levels.
In accordance with a specific embodiment of the present invention, there is provided a high-voltage generation circuit, comprising a high-voltage level detection means for detecting a high-voltage level, a high-voltage pump control means for generating a control signal responsive to a detected signal at the high-voltage level detection means, an oscillator, responsive to the control signal, for generating a pulse signal for driving a plurality of high-voltage pumps, a sequential delay means having a multiplicity of delay elements for sequentially delaying the pulse signal from the oscillator, and a plurality of high-voltage pumps for pumping high voltage under the control of a delayed pulse signal outputted from the multiplicity of delay elements in the sequential delay means and the control signal from the high-voltage level detection means.